The invention relates generally to semiconductor memories, and more particularly to a redundancy circuit for a memory and a method thereof.
As semiconductor memory devices continue to evolve, the number of individual bit cells included in the memory devices increases. A larger number of bit cells included in a memory device increases the likelihood of manufacturing faults corrupting one or more bit cells included in the memory device. In order to avoid scrapping an entire memory device due to a problem with a single bit cell, redundancy is often included in memory circuits. Redundancy allows for the replacement of defective bit cells with functional, redundant bit cells that are included in the memory device. As such, the memory will function as expected, and, as a result, production yields for the memory device are significantly increased.
One disadvantage of redundant circuitry in memory devices is the additional delay in signal paths that is introduced by the inclusion of the redundant circuitry. This additional delay can have a detrimental effect on the access time associated with the memory device. Redundant memory cells typically require longer access times than memory cells included in the memory array structures. When the overall access speed of the memory circuit is determined, the worst-case access time is used to characterize the entire memory device. Because the redundant cells included in the memory structure typically have the worst-case access time, this access time will define the overall speed with which the memory structure is expected to operate in a computing system.
When redundant cells are included in a memory structure, a potential for contention on data lines used to write data to and read data from the redundant cells may arise. This contention may be due to the inclusion of pass gates within the redundant cell selection logic. If, during one cycle, a particular redundant memory cell is enabled onto a data line (i.e. drives a state onto the data line), there is a potential for another redundant data cell to be enabled onto the same data line during the next cycle before the first data cell is able to be de-selected such that it stops driving the data line. Such data contention can lead to errors in the data values read from the memory structure. In order to ensure that such data contention is avoided, the decoding circuitry that selects particular redundant cells is skewed to perform de-selection of redundant cells more quickly than selection of redundant cells. In other words, the signal that enabled the first redundant cell to drive the data line must be de-asserted prior to any potential assertion of enabling signals that allow other redundant cells to drive the common data line.
In order to ensure that de-selection of redundant data cells occurs more rapidly than selection of redundant data cells, transistors within the selection circuitry are sized to ensure that the de-selection signals propagate through the circuitry more rapidly. Unfortunately, skewing the decoding circuitry to prefer de-selection generally reduces the speed with which the selection signals can propagate through the circuitry. Slower selection signals result in slower memory access times. As memory cell densities increase and desirable access times continue to decrease, the problems associated with the additional delays due to redundant cells become more prevalent.
Therefore, a need exists for a memory redundancy circuit that does not degrade overall memory performance.